IoT Digital Power Management and Power Integrity

Figure 1: The half-bridge output
current from each DC-DC phase
is known as the inductor current

An Internet of Things (IoT) device derives its power either from a 12-V DC supply or from a battery. In either case, power is fed to one or more power rails that operate at different voltages. These rails power the CPU and other functional blocks on the PC board. In this post, we'll take a look at how to examine an IoT's power supply for proper digital power management implementation and for power integrity.

Anatomy of an IoT Device

Figure 1: IoTs include SOCs, DDR,
DPM ICs, wireless, and MCUs

There's already more Internet of Things (IoT) devices deployed than there are humans on Earth. That gap will increase radically in coming years, and the explosion in IoT devices means a commensurate explosion in the need for debugging tools. So what's in an IoT device to debug, anyway?

Debugging the IoT

Figure 1: Chances are you're already
using the IoT in various ways

By now, we're all familiar with the phrase "Internet of Things" (IoT); some of you may be directly involved with that concept on some level as a designer/technologist. Here, we'll begin a series of posts on the IoT with some broad discussion of what it's all about, and then segue into how oscilloscopes and related hardware/software are among the best tools available for design and debug of IoT-related devices.

An Example of Three-Phase Power Measurements

Figure 1: Screen capture of a 10-s acquisition of AC input
and PWM output of a 480-V motor drive

To follow up on our last post on three-phase power calculations, and to wrap up this series of posts on the fundamentals of power, we'll walk through an example of a set of three-phase power measurements. We'll base our discussion on a single screen capture of measurements taken on a 480-V motor drive with 480-V AC input and 480-V maximum drive output. For this example, we used a Teledyne LeCroy Motor Drive Analyzer.

Three-Phase Power Calculations

Figure 1: Three-phase power calculations
entail summing of the individual
phases's power calculations

Until now, our discussions of power calculations have encompassed only single-phase systems with one voltage and one current. Now we'll turn to three-phase systems, which can be thought of as a collection of three single-phase systems. In general, three-phase power calculations are a simple summing of the individual phase power calculations and should be balanced across all three phases.

Power Calculations for Distorted Waveforms

Figure 1: The sum of many sine waves, of varying
amplitudes and frequencies, comprises the rough-
looking square wave shown in red

Our last post covered basic power calculations for pure sine waves, which are useful only up to a point in that pure sine waves are rather rare in the real world. Almost any real-world waveform carries some amount of distortion. Because distorted voltage and current waveforms comprise multiple frequencies, the relatively simple techniques used to measure power for pure, single-frequency sine waves no longer apply.

Power Calculations for Pure Sine Waves

Figure 1: For a purely resistive load,
power = voltage * current, with both vectors in phase

Wouldn't it be wonderful if every sine wave we encountered in the real world was pure, with no distortion? It sure would make life easier. Alas, it's pretty much never the case. But in reviewing sinusoidal power calculations, it's best that we begin with the simplest case: a single, pure sinusoidal line voltage and single, pure sinusoidal line current supplying a linear load.

Back to Basics: AC Sinusoidal Line Current

Figure 1: A single-phase AC current
vector rotates at 50 or 60 Hz

We've reviewed the basics of AC line voltage in previous posts. Now we'll turn our attention to the other fundamental component of line power. Regardless of whether you call it "grid," "household," "line," "utility," or "mains," AC sinusoidal current is what flows from the power utility's lines into every home and business.

More Basics of Three-Phase AC Sinusoidal Voltages

Figure 1: In the Wye three-phase
connection, neutral is present but
sometimes inaccessible

Our last post in this series on the essential principles of power covered the basics of three-phase voltages: their composition of three voltage vectors, how they're generated, how they're measured (line-line or line-neutral), and conversion of line-line values to line-neutral values. Here, we'll pick up the thread with more on three-phase AC voltages.

Transmission Lines (Part V): Reverse-Engineering the DUT

Figure 1: Every DUT can be thought of as a Thevenin
voltage source with some internal resistance

There are always two primary elements of any test and/or measurement application: the oscilloscope and the device under test (DUT). Getting valid measurement results depends, first and foremost, on the oscilloscope's capabilities given the task at hand. It also depends on what we'll call "situational awareness," or the operator's understanding of the oscilloscope and of the characteristics of the DUT.

Transmission Lines (Part IV): More Essential Principles

Figure 1: The return current in a transmission line
is as important as the signal current

In our continuing survey of the topic of transmission lines, we'd begun in our last post to cover some essential principles that govern their behavior. We're not quite done with those, so in this post we'll discuss more principles that should be part of the foundation of how you think about interconnects.

Transmission Lines (Part III): Essential Principles

Figure 1: All interconnects are transmission lines with a signal
path and a return path (not ground)

Now that we've covered some of the principles and assumptions that underlie transmission lines in two prior posts, we can now directly address the topic with some essential principles that you need to understand.

Transmission Lines (Part II): More on Bandwidth vs. Rise Time

Figure 1: In the frequency domain (right), a near-ideal
square wave displays predictable 1/f amplitude dropoff

We began this series about transmission lines by thinking about some pertinent principles and relationships that can help form our thinking about the topic. In particular, we'd covered the relationship between bandwidth and rise time and why we have this rule of thumb that says that bandwidth can be estimated using 0.35/10-90% rise time.

Transmission Lines (Part I): Introduction

Figure 1: All oscilloscopes
have a Cal output like the
one pictured here

Somewhere on the front panel of almost any oscilloscope is a "Cal" reference signal output (Figure 1). That signal is really intended for adjusting the capacitance compensation screw to calibrate a 10X high-impedance probe, but most of us know it simply as the Cal signal. Have you ever noticed that the Cal signal's rise time seems to be highly dependent on the length of the cable attached to it, and maybe even wondered why?

Probing Techniques and Tradeoffs (Part XI): Non-Ideal Situations

Figure 1: VP@Rcvr builds a transmission-line model
to virtually move less-than-ideal probing points

In using an oscilloscope to investigate transmission-line performance, we often encounter situations in which we don't have the luxury of probing at the ideal location. Fortunately, there are software tools that enable us to virtually move our probing point close to the receiver.

Probing Techniques and Tradeoffs (Part X): More Best Practices

Figure 1: Chip clips;
they're not just for
snacks anymore

In probing circuits, as with most endeavors, there are some best practices you can use to enhance your chances of obtaining optimal measurements. We began exploring this concept in our last post, and we'll continue here with more best practices.

Probing Techniques and Tradeoffs (Part IX): Best Practices

Figure 1: The typical manner
of using a hands-free probe
holder can cause issues

Having covered many of the theoretical aspects of probing signals, it's now useful to cover some best practices for high-speed active probing. We'll use some examples involving probing of DDR memory to illustrate what works best and what might not be a good idea from a practical standpoint.

Probing Techniques and Tradeoffs (Part VIII): Gain/Attenuation vs. Noise

Figure 1: Noise comparison of a
Teledyne LeCroy D1605 probe and
a competing model

When discussing oscilloscope probes and dynamic range as we've been doing of late, we must also touch upon the associated topics of internal gain/attenuation and how that relates to noise.

Probing Techniques and Tradeoffs (Part VII): More on Dynamic Range

Figure 1: Input offset range is how much
differential offset a probe can apply to
an input signal to bring it within its
differential-mode output range

In our last post in this series, we'd begun discussing the third of three types of dynamic range as applied to probes, and that is input offset range. This is the maximum differential offset that a probe can apply to the input signal to bring it within the probe's differential-mode dynamic range.

Getting The Most Out Of Your Oscilloscope: Physical-Layer Tools

Figure 1: Trigger dialog boxes will
match the protocol of interest

Debugging and validation of the physical layer of serial-data links is a preeminent oscilloscope application area these days. Today's real-time digital oscilloscopes have a wealth of tools to help you dig into any/all serial protocols and learn what's really going on electrically with your serial links.

Getting The Most Out Of Your Oscilloscope: Math Functions

Figure 1: Parameter math functions
provide a way to create custom
parameters

Parameter math functions are an important part of an oscilloscope's analysis capabilities. Using parameter math, you can create custom parameters based on simple arithmetic relationships between existing parameters. It allows you to add, subtract, multiply, divide, or rescale parameters (Figure 1).

Getting The Most Out Of Your Oscilloscope: Sequence and History Modes

Figure 1: Sequence mode grabs rare triggered events from
long captures and stores them in segments

When using an oscilloscope, there are bound to be instances in which you need to capture a large number of fast pulses in quick succession, or, conversely, a small number of events separated by long periods of time. Both are challenging for typical signal acquisition modes. But many Teledyne LeCroy oscilloscopes provide what's known as Sequence mode, which lets you capture these events while ignoring the long intervals between them.

Getting The Most Out Of Your Oscilloscope: WaveScan and XDEV Custom Parameters

Figure 1: Using WaveScan to search
for rare glitch events

In earlier posts about how to maximize your oscilloscope's utility, we've discussed how to properly capture a waveform, making measurements, and extracting more meaningful information from those measurements that might be readily apparent. Now we'll look at how to correlate anomalous behavior from a waveform with other waveforms we may have captured.

Getting The Most Out Of Your Oscilloscope: Tracks and Trends

Figure 1: The track math function
shows how data changes over time

Our discussion of cursors and parameters leads us neatly into the topics of tracks and trends, which are both means of extending parameter measurement into a more analytical direction. We can do this using math functions that are part of your Teledyne LeCroy oscilloscope's toolset.

Getting The Most Out Of Your Oscilloscope: Cursors and Parameters

Figure 1: Cursors (top) and parameter
measurements (bottom) are both
powerful tools in their own right

Oscilloscopes give us a wealth of tools with which to view, measure, and analyze the performance of a circuit. Broadly speaking, two classes of such tools are cursors and parameter measurements. Taken on their own, both classes afford the user a great deal of capability. Put them together, though, and you can really start to gain deep insights into what's going on with a waveform.

Getting The Most Out Of Your Oscilloscope: Documentation

Figure l: A LabNotebook entry quickly and easily saves
everything you need to later replicate your measurements

If we really want to get the most out of our oscilloscopes, we'd be remiss in overlooking the documentation capabilities that modern instruments provide. It's so important to document our working sessions so they're consistent and repeatable. Oscilloscope setups can be quite intricate for a given measurement or procedure. Why not let the instrument help us keep track of such things?

Getting The Most Out Of Your Oscilloscope: Trigger Delay

Figure 1: Pre-triggering, or trigger delay, is a useful tool for
debugging applications

Triggering is one of the most basic, yet most useful, tools your oscilloscope offers you. Say you want to see what led up to, and/or what follows, a trigger condition. You're looking at an interesting waveform such as that shown in Figure 1. You have the trigger's delay position set at 10% and 90%.

Getting The Most Out Of Your Oscilloscope: Navigation With MAUI

Figure 1: Oscilloscope UIs such as
Teledyne LeCroy's MAUI provide
tons of shortcuts and touch gestures

Today's real-time digital oscilloscopes are easier to use than their predecessors, and new models get easier all the time. Oscilloscopes often are equipped with touch screens and elaborate user interfaces that provide a plethora of shortcuts and smartphone-like touch gestures that make common operations extremely fast and easy.

Getting The Most Out Of Your Oscilloscope: Setup

Figure 1: Choosing a effective sample rate is key
to seeing the finer details of a waveform

Today's real-time digital oscilloscopes are so packed with bells and whistles (or "features," if you prefer) that you can forget how to use many of them. In fact, you might not even realize some exist! But they're all there for a reason, and they're all useful, maybe even more so than you know. To that end, we'll take a tour of a typical Teledyne LeCroy oscilloscope's features and give you some pointers as to how, and when, you can best take advantage of them.

Making On-Die Power-Rail Measurements (Part III)

Figure 1: This screen capture shows
the idle-state conditions

Having reviewed the test setup for on-die power-rail testing and our expectations of what the tests should show us, let's walk through the measurements and look over the results. We'll also note whether our results align with our expectations or are outside of those expectations.

Making On-Die Power-Rail Measurements (Part II)

Figure 1: When switching from low to
high, PDN noise flows from the Vdd
rail through to the Vss rail

Now that we're ready to begin some on-die power-rail measurements, it's a good idea to step back for a moment and anticipate what these measurements should show us. What actually happens on the die when CMOS gates are switching on and off? What should we expect to see on the on-die power rails? And what happens at the clock edges?

Making On-Die Power-Rail Measurements (Part I)

Figure 1: Our test setup for the
on-die measurement examples

Our exploration of on-die power-rail measurements has brought us to the point of demonstrating some examples of these measurements. As noted in the prior post, we will use an Atmel 328 microcontroller demo board, prepared with firmware to control it explicitly for our purposes, and with coaxial cable in place on the bottom of the board to serve as transmission lines for our signals of interest.

Measuring Shared On-Die Power Rails

Figure 1: This schematic represents the signal paths
in typical, general-purpose I/Os

If you're taking power-rail measurements on a semiconductor die that is appropriately instrumented with sense lines and a direct connection to the die's core PDN, you're in pretty good shape. But what if that's not the case? If the die's I/O power rails are shared by the core power rails, here's a way to get your core power-rail measurements anyway.

Setting the Stage for On-Die Power-Rail Measurements

Figure 1: Measuring on-die Vdd rail noise requires
a suitably instrumented die and package

Armed with a suitable oscilloscope and active voltage-rail probe, you're now ready to make some power-rail measurements on a semiconductor die. Of course, making measurements on a die is a little different than making measurements on a printed-circuit board. This is where careful design-for-test at the die level comes in, because the chip, its packaging, and the board on which it will be mounted must be instrumented so as to make the on-die measurements possible.

Power-Rail Noise: Small Signal, Big DC Offset

Figure 1: Your
scope's vertical
adjust has its
limits

We've been working through the various challenges in making power-rail noise measurements. One of those challenges is RF pickup that can often swamp the noise signal, and the way around that is to ensure a coaxial connection from the oscilloscope's input down to the power rail itself. We want a high signal-to-noise ratio (SNR), so we're better off with a 1X probe than with a 10X attenuating probe. We want high bandwidth, so we want a 50-Ω termination at the oscilloscope input.

Bandwidth vs. Current Load in Power-Rail Measurements

Figure 1: Connecting a 6" length of coaxial cable between
a low-impedance power rail and a 1-MΩ produces
reflections and ringing artifacts on your signal acquisition

Among the various challenges we've discussed in measuring noise on power rails are RF pickup and signal-to-noise ratio (SNR). Here's another: how do you achieve high bandwidth in your measurements while also minimizing current load on your DUT? Given that your DUT is a power rail, you really don't want to draw too much current from it. But these two measurement criteria are at loggerheads with each other. It's a quandary, and it has to do with the fundamental nature of signals on interconnects.

How 10X Attenuating Probes Kill Signal-to-Noise Ratio

Figure 1: Signal waveforms captured using a 10X attenuating
probe (top) and a BNC probe (bottom) with tips open

We've begun discussing things that can derail (see what we did there?) your power-rail measurements, such as the deleterious effects of RF interference. In the same context, one should always be mindful of certain characteristics of oscilloscope probes; namely, the 10X attenuating probes that are often lying around on the testbench.

Understand RF Pickup When Measuring Power Rails

Figure 1: Teledyne LeCroy's
HDO8108A sports a very low
noise floor of about 145 μV 

Measuring the noise on a power rail seems to be a straightforward task. However, there are some basic pitfalls that can cause incorrect, or even downright strange, results. Let's look at one of these challenges: RF pickup. We'll demonstrate the effect of RF pickup on a power-rail measurement, and then we'll show you an effective means of mitigating that effect.

Some More PCIe 3.0 Test Examples (Part II)

Figure 1: This shows how a PeRT 3 state-machine log can be invaluable
in diagnosing timeouts in requests for presets

Continuing on from our last post, let's look at some more examples of common PCIe 3.0 test scenarios and how a well-equipped PCIe 3.0 testbench would approach them. Recall, if you will, that such a testbench would comprise a real-time digital oscilloscope of suitable bandwidth (such as Teledyne LeCroy's SDA830Zi-B oscilloscope), a protocol-enabled receiver tester (such as Teledyne LeCroy's PeRT 3 Phoenix System), and software that enables simultaneous, correlated views of the protocol and physical layers (such as Teledyne LeCroy's ProtoSync software).

Some PCIe 3.0 Test Examples (Part I)

Figure 1: Protocol and electrical views of
slow electrical response to a preset request

We took a tour of a typical PCIe 3.0 testbench setup in a recent post. Now, let's see that testbench in action with some application examples of some common bad behavior one might encounter from a PCIe 3.0 channel. These include: slow electrical response, slow protocol response, and so on.

A Tour of a PCIe 3.0 Test Setup

Figure 1: Test-equipment requirements for PCIe 3.0

Having examined the complex machinations of PCIe 3.0 dynamic link equalization in earlier posts (see the links below), now we will look at a typical test setup for design and debug and/or compliance testing. Then we will move on to some test examples showing some common problems that one might encounter.

An Under-The-Hood View of PCIe 3.0 Link Training (Part II)

Figure 1: A diagrammatic view of the
PCIe 3.0 dynamic link training process

Our last post in this series began examining the recovery.equalization process of PCIe 3.0 dynamic link training, beginning with Phases 0 and 1 of the process (Figure 1). Next, we will move on to take a closer look at Phases 2 and 3, where we'll see what can happen with devices in which the algorithms are not up to par. Namely, issues such as packet errors, dropped packets, and link retraining at lower data rates than 8 Gb/s.

PCIe 4.0 PLL Bandwidth Testing

Figure 1: PLL bandwidth testing
ensures that the add-in card's
PLL bandwidth and peaking
are within specifications

The final piece of the PCIe 4.0 compliance-test puzzle—at least until PCI-SIG completes its test definitions—is the PLL bandwidth test. This test, which is performed only on add-in cards, verifies that the PLL bandwidth and peaking are within the limits allowed by the PCIe 4.0 specification (Figure 1).

PCIe 4.0 Receiver Link-Equalization Testing (Part II)

Figure 1: Working out the optimal combination of Tx emphasis
presets and receiver CTLE settings

As may be apparent from our previous post on PCIe 4.0 receiver link-equalization testing, this part of the PCIe 4.0 compliance tests is somewhat involved. When we left off last time, we were in the midst of receiver calibration, looking to ensure that the test-signal eye is as closed as possible without violating the specification limits.

PCIe 4.0 Receiver Link-Equalization Testing (Part I)

Figure 1: PCIe 4.0 receiver link-equalization testing
takes place at the site of the channel's worst-case signal

In the battery of PCIe 4.0 compliance tests, there is but a single test of receiver behavior: Rx link-equalization testing. Given that our DUT in this test is an add-in card, we want to have our worst-case signal at the Card ElectroMechanical (CEM) connector (Figure 1). The signal then proceeds through the channel on the add-in card to the end point, which is the receiver on the DUT.

PCIe 4.0 Transmitter Link-Equalization Testing

Figure 1: Shown is an overview of the PCIe 4.0
link-equalization response test

PCI Express has seen steady, and significant, increases in bit rates in each generational revision. Most recently, bit rates leaped from 8 Gb/s in PCIe 3.0 to 16 Gb/s in the current version 4.0. With these speed increases has come the need for dynamic link equalization, which becomes necessary for the sake of signal integrity. Compliance tests for dynamic link equalization is where things start to get a little more sophisticated, particularly when it comes to PCIe 4.0

PCIe 4.0 Transmitter Electrical Testing (Part II)

Figure 1: With an add-in card as our DUT, we will measure
the transmit signal at the root complex on the system board

With PCIe 4.0 compliance workshops close at hand, let's get familiar with the compliance test process. We've set the stage for electrical transmitter tests by describing the PCIe 4.0 nominal channel and also reviewed the test-equipment requirements; now we'll begin examining the tests in some detail. The two basic transmitter tests are the preset test and signal-quality test.

PCIe 4.0 Transmitter Electrical Testing (Part I)

Figure 1: The two basic PCIe 4.0 transmitter tests
are shown above outlined in green

You've been introduced to some of the background and history that has brought the PCI Express protocol standard to its fourth generation, and we've discussed the test-equipment requirements for PCIe 4.0 electrical compliance testing. Let's begin examining the compliance testing, beginning with transmitter electrical tests.

Gearing Up for PCIe 4.0 Electrical Compliance Test

Figure 1: A key element in PCIe 4.0
compliance test is a high-bandwidth,
real-time oscilloscope (shown is the
Teledyne LeCroy LabMaster 10Zi-A)

Armed with some of the background information and history on PCIe 4.0 electrical compliance testing, we're now ready to look at just what it takes in terms of test equipment to determine compliance for a PCIe 4.0 device. With the increase in data-transfer rate from 8 Gb/s in PCIe 3.0 to 16 Gb/s in PCIe 4.0, so too have the test equipment requirements advanced.

Introduction to PCIe 4.0 Electrical Compliance Test

Figure 1: PCI Express is now in its fourth generation
and poses daunting physical-layer test challenges

The Peripheral Component Interface Express standard (PCI Express, or PCIe) has been with us for some 14 years now, a pretty good run by computer-industry standards, and it shows no signs of fading away anytime soon. Now in its fourth generation, which sports data-transfer rates up to 16 Gb/s, PCIe presents daunting physical-layer test requirements (Figure 1).