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You need to test, we're here to help.

22 January 2018

Setting the Stage for On-Die Power-Rail Measurements

Measuring on-die Vdd rail noise requires a suitably instrumented die and package
Figure 1: Measuring on-die Vdd rail noise requires
a suitably instrumented die and package
Armed with a suitable oscilloscope and active voltage-rail probe, you're now ready to make some power-rail measurements on a semiconductor die. Of course, making measurements on a die is a little different than making measurements on a printed-circuit board. This is where careful design-for-test at the die level comes in, because the chip, its packaging, and the board on which it will be mounted must be instrumented so as to make the on-die measurements possible.

Power-Rail Noise: Small Signal, Big DC Offset

Your scope's vertical adjust has its limits
Figure 1: Your
scope's vertical
adjust has its
limits
We've been working through the various challenges in making power-rail noise measurements. One of those challenges is RF pickup that can often swamp the noise signal, and the way around that is to ensure a coaxial connection from the oscilloscope's input down to the power rail itself. We want a high signal-to-noise ratio (SNR), so we're better off with a 1X probe than with a 10X attenuating probe. We want high bandwidth, so we want a 50-Ω termination at the oscilloscope input.

19 January 2018

Bandwidth vs. Current Load in Power-Rail Measurements

Connecting a 6" length of coaxial cable between a low-impedance DUT and a 1-MΩ produces ringing artifacts on your signal acquisition
Figure 1: Connecting a 6" length of coaxial cable between
a low-impedance power rail and a 1-MΩ produces
reflections and ringing artifacts on your signal acquisition
Among the various challenges we've discussed in measuring noise on power rails are RF pickup and signal-to-noise ratio (SNR). Here's another: how do you achieve high bandwidth in your measurements while also minimizing current load on your DUT? Given that your DUT is a power rail, you really don't want to draw too much current from it. But these two measurement criteria are at loggerheads with each other. It's a quandary, and it has to do with the fundamental nature of signals on interconnects.

18 January 2018

How 10X Attenuating Probes Kill Signal-to-Noise Ratio

Figure 1: Signal waveforms captured using a 10X attenuating
probe (top) and a BNC probe (bottom) with tips open
We've begun discussing things that can derail (see what we did there?) your power-rail measurements, such as the deleterious effects of RF interference. In the same context, one should always be mindful of certain characteristics of oscilloscope probes; namely, the 10X attenuating probes that are often lying around on the testbench.

Understand RF Pickup When Measuring Power Rails

Teledyne LeCroy's  HDO8108A sports a very low  noise floor of about 145 μV
Figure 1: Teledyne LeCroy's
HDO8108A sports a very low
noise floor of about 145 μV 
Measuring the noise on a power rail seems to be a straightforward task. However, there are some basic pitfalls that can cause incorrect, or even downright strange, results. Let's look at one of these challenges: RF pickup. We'll demonstrate the effect of RF pickup on a power-rail measurement, and then we'll show you an effective means of mitigating that effect.

17 January 2018

Some More PCIe 3.0 Test Examples (Part II)

This shows how a PeRT 3 state-machine log can be invaluable in diagnosing timeouts in requests for presets
Figure 1: This shows how a PeRT 3 state-machine log can be invaluable
in diagnosing timeouts in requests for presets
Continuing on from our last post, let's look at some more examples of common PCIe 3.0 test scenarios and how a well-equipped PCIe 3.0 testbench would approach them. Recall, if you will, that such a testbench would comprise a real-time digital oscilloscope of suitable bandwidth (such as Teledyne LeCroy's SDA830Zi-B oscilloscope), a protocol-enabled receiver tester (such as Teledyne LeCroy's PeRT 3 Phoenix System), and software that enables simultaneous, correlated views of the protocol and physical layers (such as Teledyne LeCroy's ProtoSync software).

Some PCIe 3.0 Test Examples (Part I)

Protocol and electrical views of  slow electrical response to a preset request
Figure 1: Protocol and electrical views of
slow electrical response to a preset request
We took a tour of a typical PCIe 3.0 testbench setup in a recent post. Now, let's see that testbench in action with some application examples of some common bad behavior one might encounter from a PCIe 3.0 channel. These include: slow electrical response, slow protocol response, and so on.

A Tour of a PCIe 3.0 Test Setup

Test-equipment requirements for PCIe 3.0
Figure 1: Test-equipment requirements for PCIe 3.0
Having examined the complex machinations of PCIe 3.0 dynamic link equalization in earlier posts (see the links below), now we will look at a typical test setup for design and debug and/or compliance testing. Then we will move on to some test examples showing some common problems that one might encounter.

16 January 2018

An Under-The-Hood View of PCIe 3.0 Link Training (Part II)

A diagrammatic view of the PCIe 3.0 dynamic link training process
Figure 1: A diagrammatic view of the
PCIe 3.0 dynamic link training process
Our last post in this series began examining the recovery.equalization process of PCIe 3.0 dynamic link training, beginning with Phases 0 and 1 of the process (Figure 1). Next, we will move on to take a closer look at Phases 2 and 3, where we'll see what can happen with devices in which the algorithms are not up to par. Namely, issues such as packet errors, dropped packets, and link retraining at lower data rates than 8 Gb/s.

PCIe 4.0 PLL Bandwidth Testing

PLL bandwidth testing ensures that the add-in card's PLL bandwidth and peaking are within specifications
Figure 1: PLL bandwidth testing
ensures that the add-in card's
PLL bandwidth and peaking
are within specifications
The final piece of the PCIe 4.0 compliance-test puzzle—at least until PCI-SIG completes its test definitions—is the PLL bandwidth test. This test, which is performed only on add-in cards, verifies that the PLL bandwidth and peaking are within the limits allowed by the PCIe 4.0 specification (Figure 1).

15 January 2018

PCIe 4.0 Receiver Link-Equalization Testing (Part II)

Working out the optimal combination of Tx emphasis presets and receiver CTLE settings
Figure 1: Working out the optimal combination of Tx emphasis
presets and receiver CTLE settings
As may be apparent from our previous post on PCIe 4.0 receiver link-equalization testing, this part of the PCIe 4.0 compliance tests is somewhat involved. When we left off last time, we were in the midst of receiver calibration, looking to ensure that the test-signal eye is as closed as possible without violating the specification limits.

PCIe 4.0 Receiver Link-Equalization Testing (Part I)

PCIe 4.0 receiver link-equalization testing takes place at the site of the channel's worst-case signal
Figure 1: PCIe 4.0 receiver link-equalization testing
takes place at the site of the channel's worst-case signal
In the battery of PCIe 4.0 compliance tests, there is but a single test of receiver behavior: Rx link-equalization testing. Given that our DUT in this test is an add-in card, we want to have our worst-case signal at the Card ElectroMechanical (CEM) connector (Figure 1). The signal then proceeds through the channel on the add-in card to the end point, which is the receiver on the DUT.

PCIe 4.0 Transmitter Link-Equalization Testing

Shown is an overview of the PCIe 4.0 link-equalization response test
Figure 1: Shown is an overview of the PCIe 4.0
link-equalization response test
PCI Express has seen steady, and significant, increases in bit rates in each generational revision. Most recently, bit rates leaped from 8 Gb/s in PCIe 3.0 to 16 Gb/s in the current version 4.0. With these speed increases has come the need for dynamic link equalization, which becomes necessary for the sake of signal integrity. Compliance tests for dynamic link equalization is where things start to get a little more sophisticated, particularly when it comes to PCIe 4.0

12 January 2018

PCIe 4.0 Transmitter Electrical Testing (Part II)

With an add-in card as our DUT, we will measure the transmit signal at the root complex on the system board
Figure 1: With an add-in card as our DUT, we will measure
the transmit signal at the root complex on the system board
With PCIe 4.0 compliance workshops close at hand, let's get familiar with the compliance test process. We've set the stage for electrical transmitter tests by describing the PCIe 4.0 nominal channel and also reviewed the test-equipment requirements; now we'll begin examining the tests in some detail. The two basic transmitter tests are the preset test and signal-quality test.

PCIe 4.0 Transmitter Electrical Testing (Part I)

The two basic PCIe 4.0 transmitter tests outlined in green
Figure 1: The two basic PCIe 4.0 transmitter tests
are shown above outlined in green
You've been introduced to some of the background and history that has brought the PCI Express protocol standard to its fourth generation, and we've discussed the test-equipment requirements for PCIe 4.0 electrical compliance testing. Let's begin examining the compliance testing, beginning with transmitter electrical tests.

11 January 2018

Gearing Up for PCIe 4.0 Electrical Compliance Test

Figure 1: A key element in PCIe 4.0
compliance test is a high-bandwidth,
real-time oscilloscope (shown is the
Teledyne LeCroy LabMaster 10Zi-A)
Armed with some of the background information and history on PCIe 4.0 electrical compliance testing, we're now ready to look at just what it takes in terms of test equipment to determine compliance for a PCIe 4.0 device. With the increase in data-transfer rate from 8 Gb/s in PCIe 3.0 to 16 Gb/s in PCIe 4.0, so too have the test equipment requirements advanced.

Introduction to PCIe 4.0 Electrical Compliance Test

PCIe logo
Figure 1: PCI Express is now in its fourth generation
and poses daunting physical-layer test challenges
The Peripheral Component Interface Express standard (PCI Express, or PCIe) has been with us for some 14 years now, a pretty good run by computer-industry standards, and it shows no signs of fading away anytime soon. Now in its fourth generation, which sports data-transfer rates up to 16 Gb/s, PCIe presents daunting physical-layer test requirements (Figure 1).

04 January 2018

Probing Techniques and Tradeoffs (Part VI): Dynamic Range

Differential-mode dynamic range is the maximum allowable voltage between the probe amplifier's inputs
Figure 1: Differential-mode dynamic range is the maximum
allowable voltage between the probe amplifier's inputs
We've been discussing probe loading, which is the unavoidable reality of what happens when you attach an oscilloscope probe to a live circuit. We'll now shift the discussion to dynamic range, an important topic that can be overlooked when selecting an oscilloscope probe. There are three types of dynamic range that one should understand. Each of them will influence how you set up your probe and how you set up your signal under test to most effectively get that signal into the oscilloscope's front-end amplifier.