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Figure 1: The half-bridge output current from each DC-DC phase is known as the inductor current |
19 April 2018
IoT Digital Power Management and Power Integrity
16 April 2018
Anatomy of an IoT Device
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Figure 1: IoTs include SOCs, DDR, DPM ICs, wireless, and MCUs |
04 April 2018
Debugging the IoT
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Figure 1: Chances are you're already using the IoT in various ways |
15 March 2018
An Example of Three-Phase Power Measurements
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Figure 1: Screen capture of a 10-s acquisition of AC input and PWM output of a 480-V motor drive |
14 March 2018
Three-Phase Power Calculations
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Figure 1: Three-phase power calculations entail summing of the individual phases's power calculations |
13 March 2018
Power Calculations for Distorted Waveforms
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Figure 1: The sum of many sine waves, of varying amplitudes and frequencies, comprises the rough- looking square wave shown in red |
09 March 2018
Power Calculations for Pure Sine Waves
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Figure 1: For a purely resistive load, power = voltage * current, with both vectors in phase |
Back to Basics: AC Sinusoidal Line Current
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Figure 1: A single-phase AC current vector rotates at 50 or 60 Hz |
02 March 2018
More Basics of Three-Phase AC Sinusoidal Voltages
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Figure 1: In the Wye three-phase connection, neutral is present but sometimes inaccessible |
01 March 2018
Transmission Lines (Part V): Reverse-Engineering the DUT
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Figure 1: Every DUT can be thought of as a Thevenin voltage source with some internal resistance |
27 February 2018
Transmission Lines (Part IV): More Essential Principles
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Figure 1: The return current in a transmission line is as important as the signal current |
26 February 2018
Transmission Lines (Part III): Essential Principles
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Figure 1: All interconnects are transmission lines with a signal path and a return path (not ground) |
23 February 2018
Transmission Lines (Part II): More on Bandwidth vs. Rise Time
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Figure 1: In the frequency domain (right), a near-ideal square wave displays predictable 1/f amplitude dropoff |
20 February 2018
Transmission Lines (Part I): Introduction
Figure 1: All oscilloscopes have a Cal output like the one pictured here |
16 February 2018
Probing Techniques and Tradeoffs (Part XI): Non-Ideal Situations
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Figure 1: VP@Rcvr builds a transmission-line model to virtually move less-than-ideal probing points |
12 February 2018
Probing Techniques and Tradeoffs (Part X): More Best Practices
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Figure 1: Chip clips; they're not just for snacks anymore |
09 February 2018
Probing Techniques and Tradeoffs (Part IX): Best Practices
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Figure 1: The typical manner of using a hands-free probe holder can cause issues |
08 February 2018
Probing Techniques and Tradeoffs (Part VIII): Gain/Attenuation vs. Noise
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Figure 1: Noise comparison of a Teledyne LeCroy D1605 probe and a competing model |
06 February 2018
Probing Techniques and Tradeoffs (Part VII): More on Dynamic Range
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Figure 1: Input offset range is how much differential offset a probe can apply to an input signal to bring it within its differential-mode output range |
05 February 2018
Getting The Most Out Of Your Oscilloscope: Physical-Layer Tools
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Figure 1: Trigger dialog boxes will match the protocol of interest |
02 February 2018
Getting The Most Out Of Your Oscilloscope: Math Functions
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Figure 1: Parameter math functions provide a way to create custom parameters |
01 February 2018
Getting The Most Out Of Your Oscilloscope: Sequence and History Modes
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Figure 1: Sequence mode grabs rare triggered events from long captures and stores them in segments |
Getting The Most Out Of Your Oscilloscope: WaveScan and XDEV Custom Parameters
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Figure 1: Using WaveScan to search for rare glitch events |
31 January 2018
Getting The Most Out Of Your Oscilloscope: Tracks and Trends
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Figure 1: The track math function shows how data changes over time |
30 January 2018
Getting The Most Out Of Your Oscilloscope: Cursors and Parameters
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Figure 1: Cursors (top) and parameter measurements (bottom) are both powerful tools in their own right |
29 January 2018
Getting The Most Out Of Your Oscilloscope: Documentation
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Figure l: A LabNotebook entry quickly and easily saves everything you need to later replicate your measurements |
Getting The Most Out Of Your Oscilloscope: Trigger Delay
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Figure 1: Pre-triggering, or trigger delay, is a useful tool for debugging applications |
26 January 2018
Getting The Most Out Of Your Oscilloscope: Navigation With MAUI
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Figure 1: Oscilloscope UIs such as Teledyne LeCroy's MAUI provide tons of shortcuts and touch gestures |
Getting The Most Out Of Your Oscilloscope: Setup
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Figure 1: Choosing a effective sample rate is key to seeing the finer details of a waveform |
24 January 2018
Making On-Die Power-Rail Measurements (Part III)
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Figure 1: This screen capture shows the idle-state conditions |
Making On-Die Power-Rail Measurements (Part II)
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Figure 1: When switching from low to high, PDN noise flows from the Vdd rail through to the Vss rail |
Making On-Die Power-Rail Measurements (Part I)
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Figure 1: Our test setup for the on-die measurement examples |
Measuring Shared On-Die Power Rails
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Figure 1: This schematic represents the signal paths in typical, general-purpose I/Os |
22 January 2018
Setting the Stage for On-Die Power-Rail Measurements
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Figure 1: Measuring on-die Vdd rail noise requires a suitably instrumented die and package |
Power-Rail Noise: Small Signal, Big DC Offset
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Figure 1: Your scope's vertical adjust has its limits |
19 January 2018
Bandwidth vs. Current Load in Power-Rail Measurements
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Figure 1: Connecting a 6" length of coaxial cable between a low-impedance power rail and a 1-MΩ produces reflections and ringing artifacts on your signal acquisition |
18 January 2018
How 10X Attenuating Probes Kill Signal-to-Noise Ratio
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Figure 1: Signal waveforms captured using a 10X attenuating probe (top) and a BNC probe (bottom) with tips open |
Understand RF Pickup When Measuring Power Rails
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Figure 1: Teledyne LeCroy's HDO8108A sports a very low noise floor of about 145 μV |
17 January 2018
Some More PCIe 3.0 Test Examples (Part II)
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Figure 1: This shows how a PeRT 3 state-machine log can be invaluable in diagnosing timeouts in requests for presets |
Some PCIe 3.0 Test Examples (Part I)
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Figure 1: Protocol and electrical views of slow electrical response to a preset request |
A Tour of a PCIe 3.0 Test Setup
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Figure 1: Test-equipment requirements for PCIe 3.0 |
16 January 2018
An Under-The-Hood View of PCIe 3.0 Link Training (Part II)
Figure 1: A diagrammatic view of the PCIe 3.0 dynamic link training process |
PCIe 4.0 PLL Bandwidth Testing
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Figure 1: PLL bandwidth testing ensures that the add-in card's PLL bandwidth and peaking are within specifications |
15 January 2018
PCIe 4.0 Receiver Link-Equalization Testing (Part II)
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Figure 1: Working out the optimal combination of Tx emphasis presets and receiver CTLE settings |
PCIe 4.0 Receiver Link-Equalization Testing (Part I)
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Figure 1: PCIe 4.0 receiver link-equalization testing takes place at the site of the channel's worst-case signal |
PCIe 4.0 Transmitter Link-Equalization Testing
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Figure 1: Shown is an overview of the PCIe 4.0 link-equalization response test |
12 January 2018
PCIe 4.0 Transmitter Electrical Testing (Part II)
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Figure 1: With an add-in card as our DUT, we will measure the transmit signal at the root complex on the system board |
PCIe 4.0 Transmitter Electrical Testing (Part I)
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Figure 1: The two basic PCIe 4.0 transmitter tests are shown above outlined in green |
11 January 2018
Gearing Up for PCIe 4.0 Electrical Compliance Test
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Figure 1: A key element in PCIe 4.0 compliance test is a high-bandwidth, real-time oscilloscope (shown is the Teledyne LeCroy LabMaster 10Zi-A) |
Introduction to PCIe 4.0 Electrical Compliance Test
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Figure 1: PCI Express is now in its fourth generation and poses daunting physical-layer test challenges |
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